Owing to the advances of semiconductor manufacturing technology, the structures of semiconductor devices are further miniaturized year by year. Owing to the miniaturization of semiconductor devices, high integration can be achieved in a case of semiconductor devices having the same chip size, and reduction of chip size can be achieved in a case where the integration degree is the same.
Further, technology for mounting multiple chips three-dimensionally (three-dimensional mounting technology) has been drawing attention in recent years. With the three-dimensional mounting technology, multiple layered chips are electrically connected to each other by way of, for example, TSV (Through Silicon Via).    Patent Document 1: Japanese Laid-Open Patent Publication No. 2011-81731    Patent Document 2: Japanese Laid-Open Patent Publication No. 2010-171092
In a case of transferring, for example, clock signals throughout an entire chip, the signals are to be transferred to relatively separated areas. For example, with a semiconductor chip manufactured by using a miniaturizing process, multiple levels of buffers or the like are to be connected in a case of transferring clock signals to a relatively separated area because the absolute amount of driving current of each device of the semiconductor chip is small. Further, with miniaturized transistors, electric property or the like tends to become significantly inconsistent. Therefore, in a case of transferring clock signals throughout an entire chip, the relative timings in which clock signals are transferred deviate from each other.